RISC-V in… Typescript?

RISC-V in… Typescript?

We are accustomed to seeing RISC-V implementations in Verilog or VHDL, but [Low Level JavaScript] has one in TypeScript. Before you dismiss it as a mere emulator, know that the project relies on gateware-ts, a conversion between TypeScript and Verilog. From there, you can actually put the CPU on an FPGA. You can see the launch video below and there is one development video as well as, presumably, more to come.

We aren’t sure if many FPGA designers will be willing to switch to TypeScript. But if you are comfortable with it, it might open up FPGA development without having to learn as much of a new language.

Of course, the end product is Verilog which gets put through the vendor’s tools. The good news is that means it will work with nearly anything. The bad news is that it is another step and means things like error messages might not relate directly back to your code in a way that’s easy to understand.

There are plenty of alternatives to Verilog and VHDL, but it doesn’t seem like any of them get much traction. You might want to compare this implementation (as it develops) with a RISC-V done in SpinalHDL. Then again, maybe just learn Verilog.

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